Advanced Verification with SystemVerilog OOP Testbench

Skills you will gain

UVM Testbench Design: Build comprehensive, layered testbenches using UVM components like drivers, monitors, and sequencers.
Advanced Verification Techniques: Implement constrained-random and coverage-driven verification methods for complex designs.
UVM Component Integration: Integrate key UVM components (e.g., scoreboard, environment, agent) for modular, reusable testbenches.
Factory & Configuration Management: Utilize configuration databases and factory overrides for efficient testbench configuration and automation.
Transaction-Level Modeling (TLM): Apply TLM to simulate and model transactions effectively within a UVM-based framework.

Course Description

SystemVerilog is the industry IEEE-1800 standard combining the hardware description language and hardware verification language. This course focuses on the use of advanced verification features in SystemVerilog. Students will learn the step-by-step processes of creating flexible verification components, which form the basis of modern industry-standard methodologies such as UVM (Universal Verification Methodology). They will also gain experience developing an industrial-strength object-oriented programming (OOP) testbench that is layered, configurable, constrained-random, and coverage-driven.

The course starts with a brief review of SystemVerilog language semantics and simulation fundamentals such as event ordering, delta cycles and race conditions, which will then feed into closely related entities in program block, clocking block, and interfaces. Students will learn how to develop a complete verification environment by building flexible testbench components via the use of virtual interfaces, classes, mailboxes, dynamic arrays, and queues, etc. Functional coverage in the form of covergroup, coverpoint, and SystemVerilog Assertion (SVA), will round up the development of a complete verification environment. You will become familiar with the flexibility of an OOP-centric technique, the power of constrained random verification and the use of functional coverage tools to ensure the success of a verification project.

Concepts introduced in class are reinforced in the lab. In addition to in-class hands-on labs and weekly take-home assignments, students will work on a required project to build an advanced OOP testbench and verification environment for a selected application (such as a 10G Ethernet MAC design), with transaction-level and layered architecture. Students will form a project team, create a test plan, develop an OOP-centric verification environment, perform functional coverage, and submit a complete project report. This course builds the foundation for the course "System and Functional Verification Using UVM (Universal Verification Methodology)."

Prerequisites / Skills Needed

Skills Needed:

A course in SystemVerilog and knowledge of VHDL, Verilog, C/C++, and some hardware verification experience. Ability to install and configure open-source software on own computers.

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